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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:21:04 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:21:04 -0800 |
| commit | 53aa51dc923467bf7aed46e646640e7cee7b009d (patch) | |
| tree | bcad6288ef738cfe3e622a7952a61dd758b6e24a /techlibs/xilinx | |
| parent | 3753760971fc9cec9c09d7000e03afd3bcafe6e3 (diff) | |
| download | yosys-53aa51dc923467bf7aed46e646640e7cee7b009d.tar.gz yosys-53aa51dc923467bf7aed46e646640e7cee7b009d.tar.bz2 yosys-53aa51dc923467bf7aed46e646640e7cee7b009d.zip | |
Re-enable &mfs for synth_{ecp5,xilinx}
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b0c4795ee..e1748562e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -541,7 +541,6 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else |