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* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-194-0/+33
| | | | Fixes #2058.
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-146-761/+127
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-144-366/+5
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* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
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* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
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* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
| | | | Fixes #1822.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-2/+1
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-13/+13
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* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
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* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
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* xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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* xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
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* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
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* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
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* Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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* Fix commented out specify statementEddie Hung2020-02-271-6/+6
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* xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
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* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
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* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
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* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
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* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
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* abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-11/+12
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* abc9: cleanupEddie Hung2020-02-101-40/+40
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* Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-074-27/+22
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-53/+152
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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* xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | Part of #1550
* Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
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* Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
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* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-055-142/+375
|\ | | | | abc9: add support for required times
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