| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 |
| * | Remove sequential extension | Eddie Hung | 2019-08-20 | 6 | -359/+17 |
| * | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 |
| * | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| * | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
| * | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
| * | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
| * | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | * | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 3 | -6/+6 |
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| | | * | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
| | | * | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
| * | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 |
| * | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 |
| * | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 |
| * | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
| * | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| * | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 7 | -110/+324 |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
| * | | | | Add arrival times for SRL outputs | Eddie Hung | 2019-08-19 | 1 | -3/+5 |
| * | | | | Add BRAM arrival times | Eddie Hung | 2019-08-19 | 1 | -8/+10 |
| * | | | | Add reference to source of Tclktoq timing | Eddie Hung | 2019-08-19 | 1 | -0/+2 |
| * | | | | Add 'abc_arrival' attribute for flop outputs | Eddie Hung | 2019-08-19 | 1 | -6/+6 |
| * | | | | Update box timings | Eddie Hung | 2019-08-19 | 1 | -6/+9 |
| * | | | | Move from cell attr to module attr | Eddie Hung | 2019-08-19 | 1 | -12/+6 |
| * | | | | Use attributes instead of params | Eddie Hung | 2019-08-19 | 1 | -30/+12 |
| * | | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 12 | -25/+627 |
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| | * | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| | * | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
| | * | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 |
| | * | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
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| | * | Merge pull request #1182 from koriakin/xc6s-bram | Eddie Hung | 2019-07-11 | 9 | -8/+598 |
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| | | * | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 9 | -8/+598 |
| | * | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv... | Marcin Kościelnicki | 2019-07-11 | 2 | -6/+6 |
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| * | | Add Tsu offset to boxes, and comments | Eddie Hung | 2019-07-11 | 1 | -6/+11 |
| * | | ABC doesn't like negative delays in flop boxes... | Eddie Hung | 2019-07-11 | 1 | -6/+6 |
| * | | Fix FDCE_1 box | Eddie Hung | 2019-07-11 | 1 | -1/+1 |
| * | | Revert "$pastQ should be first input" | Eddie Hung | 2019-07-11 | 1 | -13/+13 |
| * | | Propagate INIT attr | Eddie Hung | 2019-07-11 | 1 | -5/+5 |
| * | | $pastQ should be first input | Eddie Hung | 2019-07-11 | 1 | -13/+13 |
| * | | Fix typo | Eddie Hung | 2019-07-11 | 1 | -1/+1 |
| * | | Simplify to $__ABC_ASYNC box | Eddie Hung | 2019-07-11 | 2 | -19/+8 |
| * | | $__ABC_FD_ASYNC_MUX.Q -> Y | Eddie Hung | 2019-07-11 | 1 | -1/+1 |
| * | | Restore from master | Eddie Hung | 2019-07-10 | 1 | -0/+1 |
| * | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 |
| * | | Fix clk_pol for FD*_1 | Eddie Hung | 2019-07-10 | 1 | -3/+3 |
| * | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 |
| * | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 |
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index : iCE40/yosys | |
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