aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Collapse)AuthorAgeFilesLines
* Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
| | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
* xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-232-17/+65
| | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
|
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-1/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
| | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
| | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
|
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-234-50/+50
|
* Use C++11 final/override keywords.whitequark2020-06-182-7/+7
|
* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
|
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-194-0/+33
| | | | Fixes #2058.
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
|
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
|
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
|
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-146-761/+127
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
|
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
|
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
|
* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
|
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-144-366/+5
|
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
|
* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
|
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
| | | | Fixes #1822.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-2/+1
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
| |
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-13/+13
|/
* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
|
* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
|
* xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
|
* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
|
* xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
|
* Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
|
* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
|
* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
|
* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
|
* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
|
* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
|
* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
|
* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
|
* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
|
* Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
|
* Fix commented out specify statementEddie Hung2020-02-271-6/+6
|
* xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
|
* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
|
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
|
* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
|
* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
|
* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-27 20:32:33 +0000