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* Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-211-12/+16
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| * Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
* | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
* | Fix INIT valuesEddie Hung2019-11-201-4/+4
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-1922-23020/+30968
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| * xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| * synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| * xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| * xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| * xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| * Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
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| | * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
| * | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
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| * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-5/+9
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| * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0811-112/+121
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| | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
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| * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | | CleanupEddie Hung2019-10-071-7/+2
* | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-46/+46
* | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57
* | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-054-230/+200
* | | abc -> abc9Eddie Hung2019-10-041-3/+3
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-044-181/+9
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
* | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
* | | Fix merge issuesEddie Hung2019-10-042-9/+10
* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0411-139/+154
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0411-111/+120
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* | EnglishEddie Hung2019-10-031-3/+3
* | More fixesEddie Hung2019-10-011-16/+16
* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
* | Remove need for $currQ port connectionEddie Hung2019-09-302-111/+118
* | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-308-124/+122
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| * Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
| * synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
* | Missing endmoduleEddie Hung2019-09-291-0/+1
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2911-21/+3006
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| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2911-21/+3000
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| | * Re-orderEddie Hung2019-09-271-1/+1
| | * TypoEddie Hung2019-09-261-1/+1
| | * select onceEddie Hung2019-09-261-3/+5
| | * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-1/+3
| | * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
| | * Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
| | * Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
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