| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx/ice40/ecp5: zinit requires selected wires, so select them all | Eddie Hung | 2020-05-14 | 1 | -2/+2 |
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| * | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -3/+1 |
| | | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
| * | synth_*: no need to explicitly read +/abc9_model.v | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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| * | synth_xilinx: rename dff_mode -> dff | Eddie Hung | 2020-05-14 | 1 | -8/+10 |
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| * | abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes | Eddie Hung | 2020-05-14 | 1 | -4/+1 |
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| * | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad | Eddie Hung | 2020-05-04 | 1 | -3/+5 |
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| * | Get rid of dffsr2dff. | Marcelina Kościelnicka | 2020-04-15 | 1 | -2/+1 |
| | | | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed. | ||||
| * | synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse' | Eddie Hung | 2020-04-03 | 1 | -2/+1 |
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| * | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 1 | -2/+2 |
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| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 1 | -4/+2 |
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| * | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 |
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| * | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -2/+1 |
| | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | ||||
| * | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -16/+82 |
| | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | ||||
| * | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 1 | -1/+8 |
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| * | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 1 | -1/+6 |
| | | | | | Part of #1550 | ||||
| * | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 1 | -0/+1 |
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| * | synth_xilinx: cleanup help | Eddie Hung | 2020-01-28 | 1 | -6/+4 |
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| * | synth_xilinx: fix help when no active_design; fixes #1664 | Eddie Hung | 2020-01-28 | 1 | -2/+3 |
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| * | Fix unresolved conflict from #1573 | Eddie Hung | 2020-01-28 | 1 | -1/+1 |
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| * | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+3 |
| |\ | | | | | synth_xilinx: error out if tristate without '-iopad' | ||||
| | * | Duplicate tribuf call, credit to @mwkmwkmwk | Eddie Hung | 2019-12-13 | 1 | -1/+0 |
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| | * | synth_xilinx: error out if tristate without '-iopad' | Eddie Hung | 2019-12-12 | 1 | -0/+4 |
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| * | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 | Eddie Hung | 2020-01-17 | 1 | -2/+0 |
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| * | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W | Miodrag Milanović | 2020-01-15 | 1 | -1/+1 |
| |\ \ | | | | | | | synth_xilinx: fix default W value for non-xc7 | ||||
| | * | | synth_xilinx: fix default W value for non-xc7 | Eddie Hung | 2020-01-14 | 1 | -1/+1 |
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| * | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attr | Miodrag Milanović | 2020-01-14 | 1 | -1/+1 |
| |\ \ \ | |/ / |/| | | Export wire properties in EDIF | ||||
| | * | | Use CARRY4 for abc1 as well, preventing issues with Vivado | Miodrag Milanovic | 2020-01-10 | 1 | -1/+1 |
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| * | | | Another conflict | Eddie Hung | 2020-01-11 | 1 | -1/+0 |
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| * | | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro | Eddie Hung | 2020-01-10 | 1 | -4/+11 |
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| * | | synth_xilinx -dff to work with abc too | Eddie Hung | 2020-01-02 | 1 | -6/+14 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
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| | * \ | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
| | |\ \ | | | | | | | | | "abc -dff" to no longer retime by default | ||||
| | | * | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| | | * | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | ||||
| * | | | | abc9 -keepff -> -dff; refactor dff operations | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
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| * | | | | Restore abc9 -keepff | Eddie Hung | 2020-01-01 | 1 | -1/+3 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 1 | -12/+10 |
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| | * | | | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 1 | -1/+4 |
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| | | * | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 1 | -1/+4 |
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| | * | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -2/+3 |
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| | * | | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 |
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| | * | | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 |
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| | * | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| | * | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| | |\ \ | | | | | | | | | Optimise write_xaiger | ||||
| | | * | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| * | | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -2/+14 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 1 | -4/+12 |
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index : iCE40/yosys | |
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