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techlibs
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xilinx
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synth_xilinx.cc
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Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
Eddie Hung
2019-12-30
1
-2
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+2
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abc9 -keepff -> -dff; refactor dff operations
Eddie Hung
2020-01-02
1
-3
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+3
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Restore abc9 -keepff
Eddie Hung
2020-01-01
1
-1
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+3
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
1
-12
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+10
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Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic
2019-12-28
1
-1
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+4
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
1
-1
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+4
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Addressed review comments
Miodrag Milanovic
2019-12-21
1
-2
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+3
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iopad no op for compatibility with old scripts
Miodrag Milanovic
2019-12-21
1
-0
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+3
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Make iopad option default for all xilinx flows
Miodrag Milanovic
2019-12-21
1
-14
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+5
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Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-5
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+0
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Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
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+5
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
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+5
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Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
1
-2
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+14
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
1
-4
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+12
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xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki
2019-12-18
1
-0
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+1
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xilinx: Improve flip-flop handling.
Marcin Kościelnicki
2019-12-18
1
-4
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+11
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
1
-9
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+8
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xilinx: Add tristate buffer mapping. (#1528)
Marcin Kościelnicki
2019-12-04
1
-9
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+8
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Remove clkpart
Eddie Hung
2019-12-05
1
-4
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+0
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techmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung
2019-12-03
1
-6
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+5
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clkpart -unpart into 'finalize'
Eddie Hung
2019-11-28
1
-3
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+4
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ean call after abc{,9}
Eddie Hung
2019-11-27
1
-1
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+2
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Move 'clean' from map_luts to finalize
Eddie Hung
2019-11-26
1
-1
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+1
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For abc9, run clkpart before ff_map and after abc9
Eddie Hung
2019-11-23
1
-0
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+2
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-19
1
-30
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+76
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synth_xilinx: Merge blackbox primitive libraries.
Marcin Kościelnicki
2019-11-06
1
-22
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+3
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xilinx: Add URAM288 mapping for xcup
David Shah
2019-10-23
1
-1
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+23
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xilinx: Add support for UltraScale[+] BRAM mapping
David Shah
2019-10-23
1
-1
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+6
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xilinx: Support multiplier mapping for all families.
Marcin Kościelnicki
2019-10-22
1
-8
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+45
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Call memory_dff before DSP mapping to reserve registers (fixes #1447)
N. Engelhardt
2019-10-17
1
-0
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-08
1
-5
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+9
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Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
1
-7
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+8
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Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung
2019-10-04
1
-3
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+7
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Add comment on why partial multipliers are 18x18
Eddie Hung
2019-10-04
1
-4
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+8
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Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
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+1
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Remove -D_ABC9
Eddie Hung
2019-10-07
1
-2
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+0
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abc -> abc9
Eddie Hung
2019-10-04
1
-3
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+3
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-04
1
-3
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+7
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Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
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+6
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Use read_args for read_verilog
Eddie Hung
2019-10-04
1
-3
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+6
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
Eddie Hung
2019-10-04
1
-6
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+7
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
1
-6
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+7
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-29
1
-4
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+32
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Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
1
-4
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+32
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Re-order
Eddie Hung
2019-09-27
1
-1
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+1
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Typo
Eddie Hung
2019-09-26
1
-1
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+1
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select once
Eddie Hung
2019-09-26
1
-3
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+5
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Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
1
-1
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+3
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Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
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+1
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Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
1
-2
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+0
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