| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -279/+0 |
| * | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil... | Eddie Hung | 2019-12-16 | 1 | -2/+8 |
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| | * | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 |
| * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 1 | -2/+2 |
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| * | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 1 | -8/+80 |
| * | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 1 | -0/+104 |
| * | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 1 | -0/+97 |
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index : iCE40/yosys | |
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