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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
| commit | 405e974fe51f4ede0b374ddddc398a26e04b0265 (patch) | |
| tree | 61f646fe54f9f57d18236058aca8746d8603eed8 /techlibs/xilinx/cells_sim.v | |
| parent | ece423415cbc17654c6ac81a0f4b15783c558660 (diff) | |
| parent | c0a17c2457532726b05586d3b7a030bd9f372dea (diff) | |
| download | yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.gz yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.bz2 yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 78ae23e1b..4d20e1d2c 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2107,7 +2107,7 @@ always @* begin 2'b00: XMUX <= 0; 2'b01: XMUX <= M; 2'b10: XMUX <= P; - 2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT}; + 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; default: XMUX <= 48'hxxxxxxxxxxxx; endcase end @@ -2125,8 +2125,8 @@ end // The post-adder. wire signed [48:0] X_EXT; wire signed [48:0] Z_EXT; -assign X_EXT = XMUX; -assign Z_EXT = ZMUX; +assign X_EXT = {1'b0, XMUX}; +assign Z_EXT = {1'b0, ZMUX}; assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); // Cascade outputs. |