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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
| commit | 7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f (patch) | |
| tree | ab1520d1aa2b19eb44cb46611b425431567ca0b0 /techlibs/xilinx/cells_sim.v | |
| parent | 512596760b947a9ac9088856490970d0930dd951 (diff) | |
| download | yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.gz yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.bz2 yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.zip | |
xilinx: consider DSP48E1.ADREG
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index b76055b84..63223afbf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3231,7 +3231,7 @@ module DSP48E1 ( endfunction generate - if (PREG == 0 && MREG == 0 && AREG == 0) + if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) specify (A *> P) = \A.P.comb (); (A *> PCOUT) = \A.PCOUT.comb (); @@ -3264,7 +3264,7 @@ module DSP48E1 ( $setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () ); endspecify - if (PREG == 0 && MREG == 0 && DREG == 0) + if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) specify (D *> P) = \D.P.comb (); (D *> PCOUT) = \D.PCOUT.comb (); @@ -3286,7 +3286,7 @@ module DSP48E1 ( $setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); endspecify - if (PREG || AREG || BREG || CREG || DREG || MREG) + if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG) specify if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ; if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ; |