| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 1 | -8/+15 |
| * | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| * | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 1 | -420/+445 |
| * | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 |
| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 1 | -3/+70 |
| * | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 1 | -0/+83 |
| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 1 | -81/+314 |
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| | * | abc9_ops: generate flop box ids, add abc9_required to FD* cells | Eddie Hung | 2020-01-14 | 1 | -12/+45 |
| | * | Add abc9_required to DSP48E1.{A,B,C,D,PCIN} | Eddie Hung | 2020-01-10 | 1 | -38/+117 |
| | * | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-08 | 1 | -3/+80 |
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| | * \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r... | Eddie Hung | 2020-01-06 | 1 | -59/+68 |
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| | * | | | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 1 | -24/+164 |
| * | | | | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 1 | -1/+229 |
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| * | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2020-01-06 | 1 | -51/+59 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-06 | 1 | -0/+77 |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -21/+41 |
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| | * | | | | Re-arrange FD order | Eddie Hung | 2019-12-31 | 1 | -77/+77 |
| | * | | | | FDCE ports to be alphabetical | Eddie Hung | 2019-12-31 | 1 | -3/+3 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 1 | -3/+3 |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -4/+197 |
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| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -8/+8 |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 1 | -12/+47 |
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| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 1 | -0/+797 |
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| | * | | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
| | * | | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+28 |
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| | * \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -1/+5 |
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| | * \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -0/+522 |
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| | * | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -208/+16 |
| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -47/+47 |
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| | * | | | | | | | | | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
| | * | | | | | | | | | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
| | * | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -80/+80 |
| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 1 | -0/+44 |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -0/+463 |
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| | * | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 |
| | * | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -47/+247 |
| * | | | | | | | | | | | | | | | Fix DSP48E1 sim | Eddie Hung | 2020-01-06 | 1 | -3/+3 |
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| * | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS too | Eddie Hung | 2020-01-06 | 1 | -0/+2 |
| * | | | | | | | | | | | | | | Fix return value of arrival time functions, fix word | Eddie Hung | 2020-01-06 | 1 | -18/+14 |
| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-02 | 1 | -6/+6 |
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| | * | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 |
| * | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYS | Eddie Hung | 2020-01-01 | 1 | -2/+2 |
| * | | | | | | | | | | | | | | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 1 | -0/+79 |
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| * | | | | | | | | | | | / | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 |
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| * | | | | | | | | | | | | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 1 | -3/+3 |
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| * | | | | | | | | | | | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| * | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 1 | -4/+197 |
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| * | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+35 |
| * | | | | | | | | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 |
