| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | xilinx: Add FDRSE_1, FDCPE_1. | Marcelina Kościelnicka | 2021-01-27 | 1 | -0/+80 |
| * | xilinx: Add some missing blackbox cells. | Marcelina Kościelnicka | 2020-12-21 | 1 | -0/+99 |
| * | Move signal declarations to before first use | Jeff Goeders | 2020-10-19 | 1 | -2/+2 |
| * | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) | Eddie Hung | 2020-09-23 | 1 | -17/+64 |
| * | Remove EXPLICIT_CARRY logic. | Keith Rothman | 2020-07-23 | 1 | -23/+0 |
| * | xilinx: tidy up cells_sim.v a little | Eddie Hung | 2020-05-25 | 1 | -5/+7 |
| * | xilinx: gate specify/attributes from iverilog | Eddie Hung | 2020-05-14 | 1 | -1/+3 |
| * | xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells | Eddie Hung | 2020-05-14 | 1 | -1/+19 |
| * | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -96/+126 |
| * | abc9_ops: -prep_dff_map to error if async flop found | Eddie Hung | 2020-05-14 | 1 | -4/+0 |
| * | Uncomment negative setup times; clamp to zero for connectivity | Eddie Hung | 2020-05-14 | 1 | -13/+29 |
| * | abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes | Eddie Hung | 2020-05-14 | 1 | -4/+4 |
| * | xilinx: consider DSP48E1.ADREG | Eddie Hung | 2020-03-04 | 1 | -3/+3 |
| * | xilinx: improve specify for DSP48E1 | Eddie Hung | 2020-03-04 | 1 | -32/+116 |
| * | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 |
| * | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| * | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 |
| * | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 1 | -80/+492 |
| * | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy | Eddie Hung | 2020-02-27 | 1 | -14/+12 |
| * | Fix tests by gating some specify constructs from iverilog | Eddie Hung | 2020-02-27 | 1 | -0/+16 |
| * | abc9_ops: ignore (* abc9_flop *) if not '-dff' | Eddie Hung | 2020-02-27 | 1 | -2/+6 |
| * | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 1 | -8/+15 |
| * | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| * | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 1 | -420/+445 |
| * | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 |
| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 1 | -3/+70 |
| * | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 1 | -0/+83 |
| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 1 | -81/+314 |
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| | * | abc9_ops: generate flop box ids, add abc9_required to FD* cells | Eddie Hung | 2020-01-14 | 1 | -12/+45 |
| | * | Add abc9_required to DSP48E1.{A,B,C,D,PCIN} | Eddie Hung | 2020-01-10 | 1 | -38/+117 |
| | * | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-08 | 1 | -3/+80 |
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| | * \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r... | Eddie Hung | 2020-01-06 | 1 | -59/+68 |
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| | * | | | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 1 | -24/+164 |
| * | | | | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 1 | -1/+229 |
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| * | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2020-01-06 | 1 | -51/+59 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-06 | 1 | -0/+77 |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -21/+41 |
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| | * | | | | Re-arrange FD order | Eddie Hung | 2019-12-31 | 1 | -77/+77 |
| | * | | | | FDCE ports to be alphabetical | Eddie Hung | 2019-12-31 | 1 | -3/+3 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 1 | -3/+3 |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -4/+197 |
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| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -8/+8 |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 1 | -12/+47 |
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| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 1 | -0/+797 |
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| | * | | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
| | * | | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+28 |
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| | * \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -1/+5 |
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| | * \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -0/+522 |
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