iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: improve specify functionality	Eddie Hung	2020-02-27	1	-20/+66
*	abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr	Eddie Hung	2020-02-13	1	-11/+12
*	abc9: cleanup	Eddie Hung	2020-02-10	1	-40/+40
*	Adding (* techmap_autopurge ) to FD in abc9_map.v	Eddie Hung	2020-01-14	1	-8/+8
*	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2020-01-06	1	-231/+106
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\| *	Drive $[ABCD] explicitly	Eddie Hung	2020-01-02	1	-15/+21
\| *	Rework abc9's DSP48E1 model	Eddie Hung	2020-01-01	1	-233/+102
\| *	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-20	1	-0/+78
\| *	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
* \|	Update comments	Eddie Hung	2020-01-02	1	-11/+6
* \|	abc9 -keepff -> -dff; refactor dff operations	Eddie Hung	2020-01-02	1	-55/+55
* \|	Restore abc9 -keepff	Eddie Hung	2020-01-01	1	-85/+3
* \|	Re-arrange FD order	Eddie Hung	2019-12-31	1	-83/+83
* \|	Cleanup xilinx boxes	Eddie Hung	2019-12-31	1	-0/+3
* \|	Fix incorrect $__ABC9_ASYNC[01] box	Eddie Hung	2019-12-31	1	-2/+2
* \|	Tidy up abc9_map.v	Eddie Hung	2019-12-30	1	-103/+103
* \|	Add "synth_xilinx -dff" option, cleanup abc9	Eddie Hung	2019-12-30	1	-0/+84
* \|	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-19	1	-0/+78
* \|	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	Eddie Hung	2019-12-19	1	-14/+18
* \|	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
* \|	Remove creation of $abc9_control_wire	Eddie Hung	2019-12-06	1	-16/+6
* \|	abc9 to use mergeability class to differentiate sync/async	Eddie Hung	2019-12-06	1	-12/+15
* \|	Revert "Special abc9_clock wire to contain only clock signal"	Eddie Hung	2019-12-05	1	-10/+12
* \|	Missing wire declaration	Eddie Hung	2019-12-04	1	-0/+1
* \|	abc9_map.v to transform INIT=1 to INIT=0	Eddie Hung	2019-12-04	1	-118/+201
* \|	output reg Q -> output Q to suppress warning	Eddie Hung	2019-12-04	1	-8/+8
* \|	abc9_map.v to do `zinit' and make INIT = 1'b0	Eddie Hung	2019-12-04	1	-70/+112
* \|	Add abc9_init wire, attach to abc9_flop cell	Eddie Hung	2019-12-03	1	-2/+12
* \|	Revert "Add INIT value to abc9_control"	Eddie Hung	2019-12-03	1	-8/+8
* \|	Add INIT value to abc9_control	Eddie Hung	2019-12-02	1	-8/+8
* \|	Special abc9_clock wire to contain only clock signal	Eddie Hung	2019-11-25	1	-12/+10
* \|	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	Eddie Hung	2019-11-21	1	-12/+16
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\| * \|	Do not drop async control signals in abc_map.v	Eddie Hung	2019-11-19	1	-12/+16
* \| \|	Fix INIT values	Eddie Hung	2019-11-20	1	-4/+4
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* \|	Cleanup	Eddie Hung	2019-10-07	1	-7/+2
* \|	Rename $currQ to $abc9_currQ	Eddie Hung	2019-10-07	1	-46/+46
* \|	Update comments in abc9_map.v	Eddie Hung	2019-10-07	1	-131/+57
* \|	Do not require changes to cells_sim.v; try and work out comb model	Eddie Hung	2019-10-05	1	-17/+182
* \|	Fix merge issues	Eddie Hung	2019-10-04	1	-9/+9
* \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	1	-0/+135
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*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-0/+447