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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:29:44 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:29:44 -0800 |
| commit | 35c659be74396db7824bc98428137dc9a5ac1d16 (patch) | |
| tree | 416c1085b61697c08ea3067befc028660021bed3 /techlibs/xilinx/abc9_map.v | |
| parent | 2358320f5168edd691882bba0f759d82308291d6 (diff) | |
| download | yosys-35c659be74396db7824bc98428137dc9a5ac1d16.tar.gz yosys-35c659be74396db7824bc98428137dc9a5ac1d16.tar.bz2 yosys-35c659be74396db7824bc98428137dc9a5ac1d16.zip | |
Cleanup xilinx boxes
Diffstat (limited to 'techlibs/xilinx/abc9_map.v')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index a3f9e311e..4ab8e1564 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -462,6 +462,9 @@ module FDSE_1 (output Q, input C, CE, D, S); `endif endmodule +// Attach a (combinatorial) black-box onto the output +// of thes LUTRAM primitives to capture their +// asynchronous read behaviour module RAM32X1D ( output DPO, SPO, (* techmap_autopurge *) input D, |