Add abc9_init wire, attach to abc9_flop cell

1 files changed, 12 insertions, 2 deletions

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 29ddf7133..98a4457ae 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -64,10 +64,12 @@
 //     the connectivity of its basic D-Q flop
 // (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
 //     signal, used to extract the delay target
-// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
+// (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
-// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+//     state
+// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -88,6 +90,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
@@ -103,6 +106,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
@@ -133,6 +137,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -154,6 +159,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -182,6 +188,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -203,6 +210,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -225,6 +233,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
@@ -240,6 +249,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule