| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add more DFF types | Miodrag Milanovic | 2023-04-06 | 1 | -3/+90 |
| * | Start unification effort for machxo2 and ecp5 | Miodrag Milanovic | 2023-03-20 | 1 | -6/+2 |
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 1 | -2/+2 |
| * | machxo2: Tristate is active-low. | William D. Jones | 2021-02-23 | 1 | -3/+3 |
| * | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. | William D. Jones | 2021-02-23 | 1 | -3/+3 |
| * | machxo2: synth_machxo2 now maps ports to FACADE_IO. | William D. Jones | 2021-02-23 | 1 | -0/+7 |
| * | machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. | William D. Jones | 2021-02-23 | 1 | -2/+2 |
| * | machxo2: Add dff.ys test, fix another cells_map.v typo. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| * | machxo2: Fix more oversights in machxo2 models. logic.ys test passes. | William D. Jones | 2021-02-23 | 1 | -1/+5 |
| * | machxo2: Create basic techlibs and synth_machxo2 pass. | William D. Jones | 2021-02-23 | 1 | -0/+23 |
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index : iCE40/yosys | |
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