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* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-137-122/+38
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-057-38/+122
* intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
* synth_intel_alm: Use dfflegalize.Marcelina Koƛcielnicka2020-07-042-121/+9
* Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
* intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
* intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
* intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
* Add force_downto and force_upto wire attributes.Marcelina Koƛcielnicka2020-05-192-0/+8
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+0
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1517-0/+1453