aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel
Commit message (Collapse)AuthorAgeFilesLines
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1912-0/+42
| | | | Fixes #2058.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-151-1/+0
| | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-271-1/+1
| | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-021-5/+5
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| |
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
|
* synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
|
* techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
|\
| * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
* | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
|/
* Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
|\ | | | | Assorted synth_intel cleanups from @bwidawsk
| * synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| |
| * synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| |
| * intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
|/ | | | Also fix a typo in the help message.
* synth_intel: Warn about untested Quartus backendDan Ravensloft2019-07-071-0/+3
|
* Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
|
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-282-7/+7
|
* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-2/+2
|
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-031-8/+8
|
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵c60k282018-03-317-60/+178
| | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device
* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Initial Cyclone 10 supportdh732017-11-085-1/+308
|
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
|
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
|
* Tested and working altsyncarm without init filesdh732017-10-012-57/+59
|
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-0121-0/+2721
M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 14:40:28 +0000