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| * Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| * Update box size and timingsEddie Hung2019-08-283-12/+12
| * Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
| * Put abc_* attributes above portEddie Hung2019-08-231-2/+4
| * Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-2/+8
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| | * Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
| | * Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-2/+8
| * | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
| * | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-126-150/+32
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-123-5/+5
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| * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-103-5/+5
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| | * substr() -> compare()Eddie Hung2019-08-071-3/+3
| | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
| | * stoi -> atoiEddie Hung2019-08-071-1/+1
| * | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
| * | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
| * | Add testEddie Hung2019-08-071-1/+10
| * | Remove ice40_unlutEddie Hung2019-08-072-107/+0
| * | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
* | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-1/+36
* | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
* | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-011-1/+1
* | Remove debugEddie Hung2019-07-221-1/+0
* | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
* | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
* | Indirection via $__soft_mulEddie Hung2019-07-191-0/+1
* | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
* | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| * ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| * ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| * Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| * Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
* | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
* | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-189-35/+126
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| * Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-181-2/+2
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| | * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-161-2/+2
| * | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| * | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
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| | * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
| | * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
| | * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
| | * Off by oneEddie Hung2019-07-121-1/+1
| | * Fix spacingEddie Hung2019-07-121-1/+1
| | * Remove double pushEddie Hung2019-07-121-1/+0
| | * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
| | * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
| | * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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