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* ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
* Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-221-1/+1
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| * ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
* | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
* | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
* | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
* | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
* | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-1/+1
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| * synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
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* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
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| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
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| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
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* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
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| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
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* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
* synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
* Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
* ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
* Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-204-10/+10
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-4/+4
* synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-3/+3
* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
* Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
* Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
* Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
* | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
* Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
* Added "deminout"Clifford Wolf2016-06-191-0/+1
* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
* Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-231-3/+2
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