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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 15:54:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 15:54:26 +0100 |
| commit | 2a681909dff173f63659d7c882137e53ad768ce8 (patch) | |
| tree | b0e51b09eb3ce4f1ad3e071b25bae4f43619f55e /techlibs/ice40 | |
| parent | a2154c1be0842541d04e2d9e0ebac9ccb3b472be (diff) | |
| parent | 7ff5a9db2d17c384260c2220c9205a7b4891f001 (diff) | |
| download | yosys-2a681909dff173f63659d7c882137e53ad768ce8.tar.gz yosys-2a681909dff173f63659d7c882137e53ad768ce8.tar.bz2 yosys-2a681909dff173f63659d7c882137e53ad768ce8.zip | |
Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index a2a842275..38ed45981 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -947,6 +947,7 @@ module SB_SPRAM256KA ( output reg [15:0] DATAOUT ); `ifndef BLACKBOX +`ifndef EQUIV reg [15:0] mem [0:16383]; wire off = SLEEP || !POWEROFF; integer i; @@ -973,6 +974,7 @@ module SB_SPRAM256KA ( end end `endif +`endif endmodule (* blackbox *) |