| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | gatemate: Enable register initialization | Patrick Urban | 2023-02-15 | 1 | -5/+7 |
| * | gatemate: Ensure compatibility of LVDS ports with VHDL | Patrick Urban | 2023-02-14 | 1 | -12/+12 |
| * | gatemate: Add preliminary sim models for LUT tree structures | gatecat | 2022-06-27 | 1 | -0/+44 |
| * | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 1 | -8/+0 |
| * | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 1 | -89/+85 |
| * | synth_gatemate: Remove specify blocks | Patrick Urban | 2021-11-13 | 1 | -92/+0 |
| * | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 1 | -42/+76 |
| * | synth_gatemate: Registers are uninitialized | Patrick Urban | 2021-11-13 | 1 | -2/+2 |
| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 1 | -198/+194 |
| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 1 | -101/+12 |
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 1 | -0/+1574 |
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