iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-1/+1
*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06	1	-8/+8
*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06	1	-4/+4
*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06	1	-13/+37
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	2	-0/+42
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-13/+47
*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31	1	-6/+11
*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29	1	-105/+305
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+15
*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+12
*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+14
*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18	1	-1/+1
*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18	1	-3/+3
*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18	1	-0/+22
*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17	2	-1/+26
*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31	1	-68/+38
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-4/+10
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	2	-0/+86
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-714/+40
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	4	-20/+23
*	Install simlib in datdir	Clifford Wolf	2013-11-19	1	-0/+6
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	2	-47/+43
*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07	1	-1/+7
*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06	1	-2/+14
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-11/+11
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18	1	-0/+181
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+166
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-20/+76
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	5	-0/+2643