diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 12:13:34 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 12:13:34 +0200 |
| commit | e0f693cbb09ac1a952fc49e507daefa30169bd35 (patch) | |
| tree | c3635ce8b3e472a48d74544d3fc3dd79b1ff46ea /techlibs/common | |
| parent | 5998c101a46c5121db0fa73b3af1f180a73d7fd5 (diff) | |
| download | yosys-e0f693cbb09ac1a952fc49e507daefa30169bd35.tar.gz yosys-e0f693cbb09ac1a952fc49e507daefa30169bd35.tar.bz2 yosys-e0f693cbb09ac1a952fc49e507daefa30169bd35.zip | |
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/stdcells_sim.v | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/techlibs/common/stdcells_sim.v b/techlibs/common/stdcells_sim.v index 6e5d2719a..88284a092 100644 --- a/techlibs/common/stdcells_sim.v +++ b/techlibs/common/stdcells_sim.v @@ -60,6 +60,50 @@ always @* begin end endmodule +module \$_SR_NN_ (S, R, Q); +input S, R; +output reg Q; +always @(negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; +end +endmodule + +module \$_SR_NP_ (S, R, Q); +input S, R; +output reg Q; +always @(negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; +end +endmodule + +module \$_SR_PN_ (S, R, Q); +input S, R; +output reg Q; +always @(posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; +end +endmodule + +module \$_SR_PP_ (S, R, Q); +input S, R; +output reg Q; +always @(posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; +end +endmodule + module \$_DFF_N_ (D, Q, C); input D, C; output reg Q; @@ -164,3 +208,125 @@ always @(posedge C or posedge R) begin end endmodule +module \$_DFFSR_NNN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NNP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NPN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NPP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PNN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PNP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PPN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PPP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DLATCH_N_ (E, D, Q); +input E, D; +output reg Q; +always @* begin + if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCH_P_ (E, D, Q); +input E, D; +output reg Q; +always @* begin + if (E == 1) + Q <= D; +end +endmodule + |