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author | Clifford Wolf <clifford@clifford.at> | 2014-01-18 15:35:15 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-01-18 15:35:15 +0100 |
commit | 5b96675696bb3001232b16a047cb2a9bbf8e3121 (patch) | |
tree | c5dc5227dc627655c6c529406bd03e12ba247f7c /techlibs/common | |
parent | 839af272adeb6e15c0b1fd1c35249db4a9da9f4d (diff) | |
download | yosys-5b96675696bb3001232b16a047cb2a9bbf8e3121.tar.gz yosys-5b96675696bb3001232b16a047cb2a9bbf8e3121.tar.bz2 yosys-5b96675696bb3001232b16a047cb2a9bbf8e3121.zip |
Added $bu0 cell to simlib.v
Diffstat (limited to 'techlibs/common')
-rw-r--r-- | techlibs/common/simlib.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 034244ca6..f3d652f0e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -55,6 +55,28 @@ endmodule // -------------------------------------------------------- +module \$bu0 (A, Y); + +parameter A_SIGNED = 0; +parameter A_WIDTH = 0; +parameter Y_WIDTH = 0; + +`INPUT_A +output [Y_WIDTH-1:0] Y; + +generate + if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A + assign Y[A_WIDTH-1:0] = A_BUF.val; + assign Y[Y_WIDTH-1:A_WIDTH] = 0; + end else begin:B + assign Y = +A_BUF.val; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$pos (A, Y); parameter A_SIGNED = 0; |