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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-31 11:21:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-31 11:21:29 +0100 |
| commit | ed8ad99960992a2895e0965be1b84a1fdd5e4b8b (patch) | |
| tree | 50455267651f40e37252e326e4f277382a5529df /techlibs/common | |
| parent | 36a808c572e681511400ac377fb20c598c0ed7cb (diff) | |
| download | yosys-ed8ad99960992a2895e0965be1b84a1fdd5e4b8b.tar.gz yosys-ed8ad99960992a2895e0965be1b84a1fdd5e4b8b.tar.bz2 yosys-ed8ad99960992a2895e0965be1b84a1fdd5e4b8b.zip | |
More changes to techlibs/common/simlib.v for LEC
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 07bf43d0b..c0c564fc7 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1124,14 +1124,19 @@ task tr_fetch; endtask always @(posedge pos_clk, posedge pos_arst) begin - if (pos_arst) + if (pos_arst) begin state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST]; - else + for (i = 0; i < STATE_BITS; i = i+1) + if (state_tmp[i] === 1'bz) + state_tmp[i] = 0; + state <= state_tmp; + end else begin state_tmp = next_state; - for (i = 0; i < STATE_BITS; i = i+1) - if (state_tmp[i] === 1'bz) - state_tmp[i] = 0; - state <= state_tmp; + for (i = 0; i < STATE_BITS; i = i+1) + if (state_tmp[i] === 1'bz) + state_tmp[i] = 0; + state <= state_tmp; + end end always @(state, CTRL_IN) begin |