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techlibs
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common
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mul2dsp.v
Commit message (
Expand
)
Author
Age
Files
Lines
*
Fix files with CRLF line endings
Claire Xenia Wolf
2021-06-09
1
-318
/
+318
*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
1
-2
/
+2
*
verilog: significant block scoping improvements
Zachary Snow
2021-01-31
1
-22
/
+26
*
Add force_downto and force_upto wire attributes.
Marcelina KoĆcielnicka
2020-05-19
1
-0
/
+18
*
Missing (* mul2dsp *) for sliceB
Eddie Hung
2019-09-27
1
-2
/
+2
*
Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
1
-34
/
+6
*
mul2dsp.v slice names
Eddie Hung
2019-09-25
1
-5
/
+5
*
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung
2019-09-25
1
-3
/
+1
*
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
Eddie Hung
2019-09-25
1
-2
/
+6
*
Revert "No need for $__mul anymore?"
Eddie Hung
2019-09-25
1
-8
/
+8
*
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung
2019-09-25
1
-6
/
+2
*
No need for $__mul anymore?
Eddie Hung
2019-09-25
1
-8
/
+8
*
Fix signedness bug
Eddie Hung
2019-09-20
1
-2
/
+2
*
Be sensitive to signedness
Eddie Hung
2019-09-10
1
-20
/
+21
*
Really get rid of 'opt_expr -fine' by being explicit
Eddie Hung
2019-09-10
1
-6
/
+33
*
Only swap ports if $mul and not $__mul
Eddie Hung
2019-08-13
1
-1
/
+1
*
Add DSP_A_MAXWIDTH_PARTIAL, refactor
Eddie Hung
2019-08-13
1
-144
/
+110
*
Trim Y_WIDTH
Eddie Hung
2019-08-01
1
-5
/
+3
*
Add DSP_SIGNEDONLY back
Eddie Hung
2019-08-01
1
-0
/
+16
*
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
Eddie Hung
2019-08-01
1
-4
/
+11
*
Revert "Do not do sign extension in techmap; let packer do it"
Eddie Hung
2019-08-01
1
-5
/
+14
*
Fix B_WIDTH > DSP_B_MAXWIDTH case
Eddie Hung
2019-08-01
1
-32
/
+14
*
Do not compute sign bit if result is zero
Eddie Hung
2019-07-31
1
-1
/
+2
*
For signed multipliers, compute sign bit separately...
Eddie Hung
2019-07-31
1
-23
/
+42
*
Fix spacing
Eddie Hung
2019-07-26
1
-3
/
+3
*
Add copyright header, comment on cascade
Eddie Hung
2019-07-24
1
-4
/
+34
*
Typo for Y_WIDTH
Eddie Hung
2019-07-23
1
-1
/
+1
*
Use minimum sized width wires
Eddie Hung
2019-07-22
1
-7
/
+13
*
Indirection via $__soft_mul
Eddie Hung
2019-07-19
1
-9
/
+9
*
Do not do sign extension in techmap; let packer do it
Eddie Hung
2019-07-19
1
-14
/
+5
*
Do not $mul -> $__mul if A and B are less than maxwidth
Eddie Hung
2019-07-19
1
-1
/
+3
*
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
Eddie Hung
2019-07-19
1
-28
/
+68
*
Merge branch 'xc7dsp' into ice40dsp
Eddie Hung
2019-07-19
1
-1
/
+1
|
\
|
*
Fix typo in B
Eddie Hung
2019-07-19
1
-1
/
+1
*
|
Use sign_headroom instead
Eddie Hung
2019-07-19
1
-4
/
+4
*
|
Do not define `DSP_SIGNEDONLY macro if no exists
Eddie Hung
2019-07-18
1
-4
/
+3
*
|
mul2dsp to create cells that can be interchanged with $mul
Eddie Hung
2019-07-18
1
-1
/
+7
|
/
*
Make consistent
Eddie Hung
2019-07-18
1
-1
/
+2
*
Fix signed multiplier decomposition
Eddie Hung
2019-07-18
1
-29
/
+36
*
Working for unsigned
Eddie Hung
2019-07-18
1
-52
/
+28
*
Cleanup
Eddie Hung
2019-07-18
1
-70
/
+58
*
mul2dsp: Lower partial products always have unsigned inputs
David Shah
2019-07-18
1
-31
/
+41
*
Fix mul2dsp signedness
Eddie Hung
2019-07-17
1
-42
/
+38
*
A_SIGNED == B_SIGNED so flip both
Eddie Hung
2019-07-17
1
-21
/
+12
*
Add DSP_{A,B}_SIGNEDONLY macro
Eddie Hung
2019-07-16
1
-11
/
+40
*
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung
2019-07-16
1
-22
/
+26
|
\
|
*
mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
David Shah
2019-07-16
1
-18
/
+22
|
*
mul2dsp: Fix indentation
David Shah
2019-07-16
1
-7
/
+7
*
|
Do not swap if equals
Eddie Hung
2019-07-15
1
-1
/
+1
*
|
OUT port to Y in generic DSP
Eddie Hung
2019-07-15
1
-1
/
+1
|
/
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