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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 16:51:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 16:51:31 -0700 |
| commit | 234738b103d4f2b3d937ed928fd89bc4e31627f1 (patch) | |
| tree | cf2b0c0e75232d5edf467a1605c92a664e0f083f /techlibs/common/mul2dsp.v | |
| parent | 5f8917c98491edd352dce96c63187aa814c32192 (diff) | |
| download | yosys-234738b103d4f2b3d937ed928fd89bc4e31627f1.tar.gz yosys-234738b103d4f2b3d937ed928fd89bc4e31627f1.tar.bz2 yosys-234738b103d4f2b3d937ed928fd89bc4e31627f1.zip | |
Remove _TECHMAP_CELLTYPE_ check since all $mul
Diffstat (limited to 'techlibs/common/mul2dsp.v')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 25ff28ab5..8c6a836f8 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -61,8 +61,6 @@ module _80_mul (A, B, Y); input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
- parameter _TECHMAP_CELLTYPE_ = "";
-
generate
if (0) begin end
`ifdef DSP_A_MINWIDTH
@@ -77,10 +75,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
- else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
- wire _TECHMAP_FAIL_ = 1;
`ifdef DSP_SIGNEDONLY
- else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
+ else if (!A_SIGNED)
\$mul #(
.A_SIGNED(1),
.B_SIGNED(1),
@@ -93,7 +89,7 @@ module _80_mul (A, B, Y); .Y(Y)
);
`endif
- else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
+ else if (A_WIDTH < B_WIDTH)
\$mul #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
|