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* Merge pull request #1344 from YosysHQ/eddie/ice40_signed_maccEddie Hung2019-09-011-5/+0
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| * Do not restrict multiplier to unsignedEddie Hung2019-08-301-5/+0
* | Fix select command error msg, fixes issue #1081Miodrag Milanovic2019-09-011-2/+2
* | Missing dep for test_pmgenEddie Hung2019-08-301-1/+1
* | Merge pull request #1340 from YosysHQ/eddie/abc_no_cleanEddie Hung2019-08-301-16/+10
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| * Output has priority over input when stitching in abc9Eddie Hung2019-08-291-13/+10
| * abc9 to not call "clean" at end of run (often called outside)Eddie Hung2019-08-291-3/+0
* | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-302-2/+37
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| * Fix typo that's gone unnoticed for 5 months!?!Eddie Hung2019-08-291-1/+1
| * Merge pull request #1334 from YosysHQ/clifford/async2synclatchEddie Hung2019-08-281-1/+36
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| | * Add $dlatch support to async2syncClifford Wolf2019-08-281-1/+36
* | | CleanupEddie Hung2019-08-281-4/+0
* | | Account for D port being a constantEddie Hung2019-08-281-4/+4
* | | No need to replace Q of slice since $shiftx is autoremove-dEddie Hung2019-08-281-1/+0
* | | More cleanupEddie Hung2019-08-281-12/+14
* | | More cleanupEddie Hung2019-08-281-9/+6
* | | Do not use default_params dict, hardcode default values, cleanupEddie Hung2019-08-282-25/+21
* | | Always generate if no matchEddie Hung2019-08-281-1/+1
* | | Rename test_pmgen arg xilinx_srl.{fixed,variable}Eddie Hung2019-08-281-2/+2
* | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-285-89/+457
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| * | Fix typoClifford Wolf2019-08-281-2/+2
| * | Add "paramap" passClifford Wolf2019-08-281-67/+118
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| * Merge pull request #1325 from YosysHQ/eddie/sat_initClifford Wolf2019-08-281-1/+1
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| | * Ignore all 1'bx in (* init *)Eddie Hung2019-08-271-3/+1
| | * In sat: 'x' in init attr should not override constantEddie Hung2019-08-221-0/+2
| * | improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-271-1/+12
| * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-264-32/+279
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| | * | indo -> intoEddie Hung2019-08-231-1/+1
| * | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
| * | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2348-768/+2262
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| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1641-2157/+2152
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| * | | | move attributes to wiresMarcin Kościelnicki2019-08-132-28/+9
| * | | | review fixesMarcin Kościelnicki2019-08-132-29/+4
| * | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-133-20/+356
* | | | | Missing close bracketEddie Hung2019-08-261-1/+1
* | | | | Revert "In sat: 'x' in init attr should not override constant"Eddie Hung2019-08-261-2/+0
* | | | | Remove leftover headerEddie Hung2019-08-261-1/+0
* | | | | Improve xilinx_srl.fixed generate, add .variable generateEddie Hung2019-08-261-26/+75
* | | | | Account for maxsubcnt overflowingEddie Hung2019-08-261-1/+1
* | | | | Add xilinx_srl_pm.variable to test_pmgenEddie Hung2019-08-261-0/+2
* | | | | Populate generate for xilinx_srl.fixed patternEddie Hung2019-08-261-22/+54
* | | | | Add xilinx_srl_fixed, fix typosEddie Hung2019-08-261-2/+6
* | | | | Create new $__XILINX_SHREG_ cell for variable length tooEddie Hung2019-08-231-31/+30
* | | | | Do not allow Q of last cell of variable length SRL to be (* keep *)Eddie Hung2019-08-231-0/+1
* | | | | Also add first.Q to chain_bits since variable lengthEddie Hung2019-08-231-0/+1
* | | | | Do not enforce !EN_POLARITY on $dffeEddie Hung2019-08-231-2/+0
* | | | | Create new cell for fixed length SRLEddie Hung2019-08-231-14/+22
* | | | | Cleanup FDRE matchingEddie Hung2019-08-231-45/+19
* | | | | Oops don't need a finally blockEddie Hung2019-08-231-5/+0
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