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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 17:25:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 17:25:30 -0700 |
| commit | 188b49378a47c7bfc311b4e439ac74635ba85a77 (patch) | |
| tree | c04376d64f40314aa9ee3232485899f5ff5c93a6 /passes | |
| parent | e081303ee895f2f65465e930d0df8c92fc26c058 (diff) | |
| download | yosys-188b49378a47c7bfc311b4e439ac74635ba85a77.tar.gz yosys-188b49378a47c7bfc311b4e439ac74635ba85a77.tar.bz2 yosys-188b49378a47c7bfc311b4e439ac74635ba85a77.zip | |
Create new cell for fixed length SRL
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 36 |
1 files changed, 22 insertions, 14 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index c0c827a25..e1d38d7bd 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -67,32 +67,40 @@ void run_fixed(xilinx_srl_pm &pm) pm.autoremove(cell); } - Cell *c = first_cell; - SigBit Q = st.first->getPort(ID(Q)); - c->setPort(ID(Q), Q); + auto last_cell = ud.longest_chain.front(); + Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + pm.module->swap_names(c, first_cell); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { - c->parameters.clear(); + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); c->setParam(ID(INIT), initval.as_const()); - if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); - else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) + else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) c->setParam(ID(CLKPOL), 0); - else if (c->type.in(ID(FDRE))) - c->setParam(ID(CLKPOL), param_def(c, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); + else if (first_cell->type.in(ID(FDRE))) + c->setParam(ID(CLKPOL), param_def(first_cell, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); else log_abort(); - if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) c->setParam(ID(ENPOL), 1); - else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) c->setParam(ID(ENPOL), 0); else c->setParam(ID(ENPOL), 2); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) - c->setPort(ID(E), State::S1); + + c->setPort(ID(C), first_cell->getPort(ID(C))); + c->setPort(ID(D), first_cell->getPort(ID(D))); + c->setPort(ID(Q), last_cell->getPort(ID(Q))); c->setPort(ID(L), GetSize(ud.longest_chain)-1); - c->type = ID($__XILINX_SHREG_); + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) + c->setPort(ID(E), State::S1); + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setPort(ID(E), first_cell->getPort(ID(E))); + else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) + c->setPort(ID(E), first_cell->getPort(ID(CE))); + else + log_abort(); } else log_abort(); |