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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:42:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:43:08 -0700 |
| commit | 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d (patch) | |
| tree | 2a70d1550ab81a96f4c383524fd4c66bdef2c7b0 /passes | |
| parent | c50d68653d093a8daa47f589836e6178be82b54f (diff) | |
| download | yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.gz yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.bz2 yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.zip | |
In sat: 'x' in init attr should not override constant
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..bcc690fa3 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,6 +268,8 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); + if (bit.is_fully_const() && rhs[i] == State::Sx) + rhs[i] = bit; if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); |