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author | Marcin KoĆcielnicki <marcin@symbioticeda.com> | 2019-08-27 17:26:47 +0200 |
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committer | Marcin KoĆcielnicki <marcin@symbioticeda.com> | 2019-08-27 17:26:47 +0200 |
commit | 5fb4b12cb50b870b546d76f9c702678d8f0aa60a (patch) | |
tree | 856ddb83348e3a06076e42d79055067599ca3fe0 /passes | |
parent | 528f1c86877d247700bd9445e03c85b3eb437b5c (diff) | |
download | yosys-5fb4b12cb50b870b546d76f9c702678d8f0aa60a.tar.gz yosys-5fb4b12cb50b870b546d76f9c702678d8f0aa60a.tar.bz2 yosys-5fb4b12cb50b870b546d76f9c702678d8f0aa60a.zip |
improve clkbuf_inhibit propagation upwards through hierarchy
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/clkbufmap.cc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 82b3dcdf7..246932d81 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -166,13 +166,24 @@ struct ClkbufmapPass : public Pass { // Insert buffers. std::vector<pair<Wire *, Wire *>> input_queue; - for (auto wire : module->selected_wires()) + // Copy current wire list, as we will be adding new ones during iteration. + std::vector<Wire *> wires(module->wires()); + for (auto wire : wires) { // Should not happen. if (wire->port_input && wire->port_output) continue; + bool process_wire = module->selected(wire); if (!select && wire->get_bool_attribute("\\clkbuf_inhibit")) + process_wire = false; + if (!process_wire) { + // This wire is supposed to be bypassed, so make sure we don't buffer it in + // some buffer higher up in the hierarchy. + if (wire->port_output) + for (int i = 0; i < GetSize(wire); i++) + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); continue; + } pool<int> input_bits; |