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| | | * | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-074-41/+54
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| | | * | | Remove std:: namespaceEddie Hung2019-08-071-5/+5
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| | | * | | stoi -> atoiEddie Hung2019-08-0734-110/+110
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| | | * | | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
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| | | * | | Fix typosEddie Hung2019-08-061-5/+5
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| | | * | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-0631-100/+100
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| | | * | | Use IdString::begins_with()Eddie Hung2019-08-062-19/+17
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| | | * | | Use State::S{0,1}Eddie Hung2019-08-066-12/+12
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| | | * | | Make liberal use of IdString.in()Eddie Hung2019-08-0614-34/+34
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| | | * | | Cleanup opt_expr.ccEddie Hung2019-08-061-35/+30
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| | * | | | Merge pull request #1276 from YosysHQ/clifford/fix1273Clifford Wolf2019-08-101-15/+54
| | |\ \ \ \ | | | | | | | | | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
| | | * | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵Clifford Wolf2019-08-091-15/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | Merge pull request #1267 from whitequark/proc_prune-fix-1243whitequark2019-08-091-9/+7
| | |\ \ \ \ \ | | | |/ / / / | | |/| | | | proc_prune: fix handling of exactly identical assigns
| | | * | | | proc_prune: fix handling of exactly identical assigns.whitequark2019-08-081-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
| * | | | | | Wrong way aroundEddie Hung2019-08-101-2/+2
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| * | | | | | cover_list -> cover as per @cliffordwolfEddie Hung2019-08-101-2/+2
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| * | | | | | GrammarEddie Hung2019-08-091-1/+1
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| * | | | | | Separate $alu handlingEddie Hung2019-08-091-7/+50
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| * | | | | | opt_expr -fine to trim LSBs of $alu tooEddie Hung2019-08-091-4/+9
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| * | | | | Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
| |\ \ \ \ \ | | | | | | | | | | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
| | * | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
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| * / / / / Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-0/+111
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| * | | | Add commentEddie Hung2019-08-071-2/+3
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| * | | | Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| * | | | Add TODOEddie Hung2019-08-071-0/+2
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| * | | | Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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| * | | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-072-3/+28
| |\ \ \ | | | | | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| | * | | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
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| | * | | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-067-43/+118
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| | * | | Try and fix againEddie Hung2019-07-191-5/+4
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| | * | | Do not access beyond boundsEddie Hung2019-07-191-1/+1
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| | * | | Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
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| | * | | Remove "top" from messageEddie Hung2019-07-191-1/+1
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| | * | | Also optimise MSB of $subEddie Hung2019-07-191-3/+3
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| | * | | wreduce for $subEddie Hung2019-07-191-0/+23
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| * | | | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-071-16/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Redesign of cell cost APIClifford Wolf2019-08-071-22/+20
| | |/ / | |/| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-063-29/+67
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #1242 from jfng/fix-proc_prune-partialwhitequark2019-08-031-2/+11
| |\ \ \ | | | | | | | | | | proc_prune: Promote partially redundant assignments.
| | * | | proc_prune: Promote partially redundant assignments.Jean-François Nguyen2019-08-011-2/+11
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| * | | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-0/+1
| |\ \ \ | | | | | | | | | | Visual Studio build fix
| | * | | Visual Studio build fixMiodrag Milanovic2019-07-311-0/+1
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| * / / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-10/+10
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| * / Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-161-44/+127
| |\ | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
| | * Add commentEddie Hung2019-07-131-0/+5
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| | * duplicate -> cloneEddie Hung2019-07-121-3/+3
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| | * More cleanupEddie Hung2019-07-121-8/+2
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| | * CleanupEddie Hung2019-07-121-29/+51
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| | * CleanupEddie Hung2019-07-121-10/+4
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