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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:58:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:58:50 -0700 |
| commit | cb0fd0521531a69632102f5fad8cdc9996ed4dee (patch) | |
| tree | 6342bf0f28d5836bba1bcfd85398135406f90f81 /passes | |
| parent | 54708dfbd786032e841f48f15af4875c1eabbbfe (diff) | |
| download | yosys-cb0fd0521531a69632102f5fad8cdc9996ed4dee.tar.gz yosys-cb0fd0521531a69632102f5fad8cdc9996ed4dee.tar.bz2 yosys-cb0fd0521531a69632102f5fad8cdc9996ed4dee.zip | |
Do not access beyond bounds
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/wreduce.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 294f0d57e..908a85d5b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -372,7 +372,7 @@ struct WreduceWorker int i; for (i = 0; i < GetSize(sig); i++) { - if (B[i] != S0 && (sub || A[i] != S0)) + if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0)) break; if (B[i] == S0) module->connect(sig[i], A[i]); |