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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 13:12:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 13:15:02 -0700 |
| commit | f69410daaf68cd3cef5e365df9b27c623ce589a7 (patch) | |
| tree | 704d8272db98f34d0ba02e3e074a4bda2823901a /passes | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| download | yosys-f69410daaf68cd3cef5e365df9b27c623ce589a7.tar.gz yosys-f69410daaf68cd3cef5e365df9b27c623ce589a7.tar.bz2 yosys-f69410daaf68cd3cef5e365df9b27c623ce589a7.zip | |
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_lut.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 587ef878a..4c199ba72 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -101,6 +101,12 @@ struct OptLutWorker { if (cell->type == "$lut") { + if (cell->has_keep_attr()) + continue; + SigBit lut_output = cell->getPort("\\Y"); + if (lut_output.wire->get_bool_attribute("\\keep")) + continue; + int lut_width = cell->getParam("\\WIDTH").as_int(); SigSpec lut_input = cell->getPort("\\A"); int lut_arity = 0; |