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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-10 11:55:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-10 11:55:00 -0700 |
| commit | 282cc77604a9a855c303869321d4179790b0b64b (patch) | |
| tree | bb8148c6915cd7ee1df185b4c63feaff02bd7cac /passes | |
| parent | 02b0d328ad4eadd2011344ef30e718262932cff8 (diff) | |
| download | yosys-282cc77604a9a855c303869321d4179790b0b64b.tar.gz yosys-282cc77604a9a855c303869321d4179790b0b64b.tar.bz2 yosys-282cc77604a9a855c303869321d4179790b0b64b.zip | |
Wrong way around
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index c803b5d3d..29510fe81 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); @@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover_list("opt.opt_expr.fine.$alu"); + cover("opt.opt_expr.fine.$alu"); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\X", sig_x.extract_end(i)); |