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Age
Files
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-12
1
-8
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+67
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Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Eddie Hung
2019-12-09
1
-8
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+67
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ice40_wrapcarry -unwrap to preserve 'src' attribute
Eddie Hung
2019-12-09
1
-1
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+9
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-unwrap to create $lut not SB_LUT4 for opt_lut
Eddie Hung
2019-12-09
1
-7
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+5
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Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
Eddie Hung
2019-12-09
1
-7
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+11
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ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung
2019-12-09
1
-17
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+55
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Drop keep=0 attributes on SB_CARRY
Eddie Hung
2019-12-06
1
-0
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+8
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Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
Eddie Hung
2019-12-05
1
-0
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+1
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ice40_wrapcarry to preserve SB_CARRY's attributes
Eddie Hung
2019-12-03
1
-0
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+2
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
2
-175
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+137
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iopadmap: Refactor and fix tristate buffer mapping. (#1527)
Marcin Kościelnicki
2019-12-04
1
-146
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+97
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abc9: Fix breaking of SCCs
David Shah
2019-12-01
1
-29
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+40
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Call abc9 with "&write -n", and parse_xaiger() to cope
Eddie Hung
2019-12-06
1
-2
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+2
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Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
Eddie Hung
2019-12-06
1
-39
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+15
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abc9 to do clock partitioning again
Eddie Hung
2019-12-05
1
-37
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+144
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Remove clkpart
Eddie Hung
2019-12-05
2
-309
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+0
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Add assertion
Eddie Hung
2019-12-03
1
-0
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+1
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Add abc9_init wire, attach to abc9_flop cell
Eddie Hung
2019-12-03
1
-2
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+12
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Cleanup
Eddie Hung
2019-12-01
1
-3
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+2
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Use pool instead of std::set for determinism
Eddie Hung
2019-12-01
1
-1
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+1
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Use pool<> not std::set<> for determinism
Eddie Hung
2019-12-01
1
-4
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+4
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-28
1
-1
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+1
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Move \init signal for non-port signals as long as internally driven
Eddie Hung
2019-11-28
1
-1
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+1
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Fix multiple driver issue
Eddie Hung
2019-11-27
1
-2
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+7
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Fix multiple driver issue
Eddie Hung
2019-11-27
1
-2
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+7
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-27
3
-7
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+18
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Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
Eddie Hung
2019-11-27
1
-3
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+3
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Check for either sign or zero extension for postAdd packing
Eddie Hung
2019-11-26
1
-3
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+3
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Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
Clifford Wolf
2019-11-27
1
-0
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+4
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memory_collect: Copy attr from RTLIL::Memory to cell
David Shah
2019-11-18
1
-0
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+4
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opt_share: Fix handling of fine cells.
Marcin Kościelnicki
2019-11-27
1
-4
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+11
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-7
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+3
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Do not replace constants with same wire
Eddie Hung
2019-11-27
1
-7
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+3
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-47
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+71
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Cleanup
Eddie Hung
2019-11-27
1
-5
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+3
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*
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Check for nullptr
Eddie Hung
2019-11-27
1
-1
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+1
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Stray log_dump
Eddie Hung
2019-11-27
1
-1
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+0
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Revert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung
2019-11-27
1
-40
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+71
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Promote output wires in sigmap so that can be detected
Eddie Hung
2019-11-26
1
-8
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+4
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Fix submod -hidden
Eddie Hung
2019-11-26
1
-5
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+6
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Add -hidden option to submod
Eddie Hung
2019-11-26
1
-11
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+25
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Update docs with bullet points
Eddie Hung
2019-11-26
1
-10
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+9
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Move \init from source wire to submod if output port
Eddie Hung
2019-11-25
1
-0
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+7
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Fix submod -hidden
Eddie Hung
2019-11-26
1
-5
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+6
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clkpart to use 'submod -hidden'
Eddie Hung
2019-11-26
1
-1
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+1
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Add -hidden option to submod
Eddie Hung
2019-11-26
1
-20
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+40
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Fix debug
Eddie Hung
2019-11-25
1
-3
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+3
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
1
-0
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+41
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-0
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+41
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abc9 to contain time call
Eddie Hung
2019-11-25
1
-1
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+1
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