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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:39:14 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:39:14 -0800 |
| commit | 969f51141535ac70d8fbb2a0e2da7ee2aba833b8 (patch) | |
| tree | f1183177691e18d3ee5527aaa5fc8cce1baf6f59 /passes | |
| parent | 6318e3ce6df2484c4cc17856608e2a6354cd643a (diff) | |
| download | yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.tar.gz yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.tar.bz2 yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.zip | |
Promote output wires in sigmap so that can be detected
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 14974666e..f23dfb702 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -34,7 +34,6 @@ struct SubmodWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap; - pool<SigBit> outputs; bool copy_mode; bool hidden_mode; @@ -124,13 +123,13 @@ struct SubmodWorker for (auto &it : bit_flags) { - const RTLIL::SigBit &bit = it.first; + const RTLIL::SigBit &bit = sigmap(it.first); RTLIL::Wire *wire = bit.wire; bit_flags_t &flags = it.second; if (wire->port_input) flags.is_ext_driven = true; - if (outputs.count(bit)) + if (wire->port_output) flags.is_ext_used = true; bool new_wire_port_input = false; @@ -240,11 +239,8 @@ struct SubmodWorker for (auto port : module->ports) { auto wire = module->wire(port); - if (!wire->port_output) - continue; - for (auto b : sigmap(wire)) - if (b.wire) - outputs.insert(b); + if (wire->port_output) + sigmap.add(wire); } if (opt_name.empty()) |