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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:51:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:51:39 -0800 |
| commit | cb05fe0f70039077bdc1c72f0e2121be6eb7835b (patch) | |
| tree | 3948d7c879a008a6a050c3a918014c3c47056d76 /passes | |
| parent | d960feeeb056a19c722ea9e17c85e2725d76a685 (diff) | |
| download | yosys-cb05fe0f70039077bdc1c72f0e2121be6eb7835b.tar.gz yosys-cb05fe0f70039077bdc1c72f0e2121be6eb7835b.tar.bz2 yosys-cb05fe0f70039077bdc1c72f0e2121be6eb7835b.zip | |
Check for nullptr
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 349483778..7b5e110cb 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -141,7 +141,7 @@ struct SubmodWorker else { auto sig = sigmap(wire); for (auto c : sig.chunks()) - if (c.wire->port_output) { + if (c.wire && c.wire->port_output) { flags.is_ext_used = true; break; } |