| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Move Pass::call() out of abc9_ops into abc9 | Eddie Hung | 2019-12-30 | 2 | -68/+59 |
| * | Use function arg | Eddie Hung | 2019-12-30 | 1 | -9/+9 |
| * | holes_module to be whitebox | Eddie Hung | 2019-12-30 | 1 | -0/+10 |
| * | Add abc9_ops -prep_holes | Eddie Hung | 2019-12-30 | 2 | -3/+313 |
| * | Add abc9_ops -prep_dff | Eddie Hung | 2019-12-30 | 3 | -39/+50 |
| * | Restore count_outputs, move process check to abc | Eddie Hung | 2019-12-30 | 2 | -11/+13 |
| * | Fix struct name | Eddie Hung | 2019-12-30 | 1 | -3/+3 |
| * | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2019-12-30 | 2 | -323/+124 |
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| | * | write_xaiger to use scratchpad for stats; cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -173/+15 |
| | * | Remove submod changes | Eddie Hung | 2019-12-30 | 1 | -99/+37 |
| | * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 6 | -101/+1080 |
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| | * | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -49/+19 |
| | * | | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
| | * | | Disable clock domain partitioning in Yosys pass, let ABC do it | Eddie Hung | 2019-12-23 | 1 | -6/+22 |
| | * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 2 | -20/+19 |
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| | * | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -5/+5 |
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 5 | -4/+245 |
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| | * | | | | Remove &verify -s | Eddie Hung | 2019-12-17 | 1 | -1/+1 |
| | * | | | | Use pool<> instead of std::set<> to preserver ordering | Eddie Hung | 2019-12-17 | 1 | -6/+6 |
| | * | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 1 | -8/+67 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -175/+137 |
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| | * | | | | | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -2/+2 |
| | * | | | | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 |
| | * | | | | | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 |
| | * | | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 2 | -309/+0 |
| | * | | | | | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 |
| | * | | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
| | * | | | | | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 |
| | * | | | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 |
| | * | | | | | | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 |
| | * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| | | * | | | | | | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
| | | * | | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
| | * | | | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -7/+18 |
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| | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| | | * | | | | | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
| | * | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -47/+71 |
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| | | * | | | | | | | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
| | | * | | | | | | | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
| | | * | | | | | | | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
| | | * | | | | | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -40/+71 |
| | | * | | | | | | | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
| | | * | | | | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
| | | * | | | | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
| | | * | | | | | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
| | | * | | | | | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
| | * | | | | | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
| | * | | | | | | | | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
