iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...	Clifford Wolf	2014-03-11	1	-2/+3
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	4	-3/+11
*	Fixed memory corruption in passes/abc/blifparse.cc	Clifford Wolf	2014-03-11	1	-1/+1
*	Fixed dumping of timing() { .. } block in libparse	Clifford Wolf	2014-03-09	1	-2/+3
*	Verbose reading of liberty and constr files in ABC pass	Clifford Wolf	2014-03-09	1	-2/+2
*	Fixed bug in freduce command	Clifford Wolf	2014-03-07	1	-0/+30
*	Some minor code cleanups in freduce command	Clifford Wolf	2014-03-07	1	-5/+5
*	Added freduce -dump	Clifford Wolf	2014-03-06	1	-1/+24
*	Added freduce -stop	Clifford Wolf	2014-03-06	1	-3/+18
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06	1	-2/+2
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03	1	-2/+2
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-0/+1
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22	1	-1/+1
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21	1	-2/+6
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20	1	-0/+79
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20	1	-10/+30
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	1	-8/+45
*	Added connwrappers command	Clifford Wolf	2014-02-20	2	-0/+206
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18	1	-49/+93
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\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18	1	-5/+34
\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18	1	-31/+31
\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18	1	-14/+29
* \|	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
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*	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	Clifford Wolf	2014-02-17	1	-5/+9
*	Added "-dump_fail_to_vcd" argument to SAT solver	Andrew Zonenberg	2014-02-17	1	-0/+114
*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16	1	-2/+2
*	Fixed use of selection in splitnets command	Clifford Wolf	2014-02-16	1	-1/+1
*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
*	Added != support for relational select pattern	Clifford Wolf	2014-02-16	1	-1/+7
*	Added iopadmap -bits	Clifford Wolf	2014-02-15	1	-14/+48
*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
*	Fixed opt_const handling of double invert with non-1 output width	Clifford Wolf	2014-02-15	1	-1/+1
*	Added abc -keepff option	Clifford Wolf	2014-02-14	1	-5/+18
*	updated default ABC command strings	Clifford Wolf	2014-02-13	1	-4/+4
*	Updated ABC	Clifford Wolf	2014-02-13	1	-0/+23
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-7/+19
*	Removed double blanks in ABC default command sequences	Clifford Wolf	2014-02-13	1	-4/+4
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13	1	-10/+31
*	Updated ABC to rev e97a6e1d59b9	Clifford Wolf	2014-02-12	1	-4/+49
*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09	1	-36/+119
*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09	1	-5/+36
*	Bugfix in delete command	Clifford Wolf	2014-02-09	1	-1/+3
*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08	1	-0/+1
*	Build fixes for log cmd	Clifford Wolf	2014-02-08	1	-2/+2
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-08	2	-0/+79
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