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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 23:34:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 23:34:45 +0100 |
| commit | 8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90 (patch) | |
| tree | 477f348cb53cd4b15eaa1088e3cfe3d694b8800f /passes | |
| parent | 0a60f95224376304565d950832f8320d5f4fb70e (diff) | |
| download | yosys-8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90.tar.gz yosys-8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90.tar.bz2 yosys-8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90.zip | |
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/proc/proc_arst.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 571946573..057378e7c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -156,8 +156,12 @@ restart_proc_arst: if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); - sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + if (proc->syncs.size() == 1) { + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + } else { + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width); |