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* Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-051-1/+16
|\ | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-2829-1488/+3392
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| * | Add $_FF_ and $_SR* courtesy of @mwkmwkmwkEddie Hung2019-12-201-4/+6
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| * | More stringent check for flop cellsEddie Hung2019-12-201-2/+4
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| * | opt_merge to discard \init of '$' cells with 'Q' port when mergingEddie Hung2019-12-131-0/+11
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* | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+1
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* | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-051-6/+77
|\ \ \ | | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-151-6/+77
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* | | | Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-053-77/+383
|\ \ \ \ | | | | | | | | | | abc9: add support for required times
| * | | | abc9_ops: -check for negative arrival/required timesEddie Hung2020-01-271-4/+22
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| * | | | Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-279-107/+361
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| * | | | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+4
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| * | | | | abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)Eddie Hung2020-01-141-2/+2
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| * | | | | abc9_ops: -check to check abc9_{arrival,required}Eddie Hung2020-01-141-3/+30
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| * | | | | abc9_ops: implement a requireds_cacheEddie Hung2020-01-141-26/+34
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| * | | | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-65/+56
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| * | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-141-9/+0
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | abc9_ops: fix -reintegrate handling of $__ABC9_DELAYEddie Hung2020-01-141-2/+3
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| * | | | | | abc9_ops: -prep_times -> -prep_delays; add docEddie Hung2020-01-142-11/+23
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| * | | | | | abc9_ops: cleanupEddie Hung2020-01-141-14/+5
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| * | | | | | abc9_ops: discard $__ABC9_DELAY boxesEddie Hung2020-01-141-7/+2
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| * | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-145-249/+277
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-123-131/+121
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | | | log_debug() for abc9_{arrival,required} timesEddie Hung2020-01-101-1/+7
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| * | | | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-101-17/+67
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| * | | | | | | | abc9_ops -prep_times: update commentEddie Hung2020-01-101-3/+4
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| * | | | | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-102-75/+251
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| * | | | | | | | abc9_exe: -box to not require -lutEddie Hung2020-01-091-9/+4
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* | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-032-0/+279
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* | | | | | | | | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonlyDavid Shah2020-02-021-0/+7
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | synth_xilinx: add -dsp-multonly
| * | | | | | | | | xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | abc9: restore ability to use ABCEXTERNALGabriel Somlo2020-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
* | | | | | | | | | Merge branch 'vector_fix' of https://github.com/Kmanfi/yosysClaire Wolf2020-01-291-1/+3
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also some minor fixes to the original PR.
| * | | | | | | | | | Fix input vector for reduce cells. Infinite loop fixed.Kaj Tuomi2017-10-171-0/+2
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* | | | | | | | | | | Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-checkClaire Wolf2020-01-291-1/+2
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cell
| * | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cellDavid Shah2020-01-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-281-1/+1
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like Verilog...
* | | | | | | | | | | | Merge pull request #1567 from YosysHQ/eddie/sat_init_warningClaire Wolf2020-01-281-1/+2
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
| * | | | | | | | | | | | Suppress warning message for init[i] = 1'bxEddie Hung2019-12-111-1/+2
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* | | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-1/+5
|\ \ \ \ \ \ \ \ \ \ \ \ | |_|_|/ / / / / / / / / |/| | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'
| * | | | | | | | | | | tribuf: set scratchpad boolean 'tribuf.added_something'Eddie Hung2019-12-121-1/+5
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* | / / / / / / / / / redirect fuser stderr to /dev/nullPepijn de Vos2020-01-281-1/+1
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* | | | | | | | | | Merge pull request #1619 from YosysHQ/eddie/abc9_refactorEddie Hung2020-01-274-886/+1480
|\ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|/ / | |/| | | | | | | | Refactor `abc9` pass
| * | | | | | | | | abc9_ops: add commentsEddie Hung2020-01-271-1/+13
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| * | | | | | | | | abc9: -reintegrate recover type from existing cell, check against boxidEddie Hung2020-01-231-30/+19
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| * | | | | | | | | abc9: warning message if no modules selectedEddie Hung2020-01-231-0/+6
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