Merge pull request #1576 from YosysHQ/eddie/opt_merge_init

opt_merge: discard \init of '$' cells with 'Q' port when merging

1 files changed, 16 insertions, 1 deletions

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index aaea6159e..8823a9061 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,9 @@ struct OptMergeWorker
 			return true;
 		}
 
-		if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
+		if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+					cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+					cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
 			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
 			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
@@ -323,6 +325,19 @@ struct OptMergeWorker
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
+
+							if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+										cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+										cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+								for (auto c : it.second.chunks()) {
+									auto jt = c.wire->attributes.find(ID(init));
+									if (jt == c.wire->attributes.end())
+										continue;
+									for (int i = c.offset; i < c.offset + c.width; i++)
+										jt->second[i] = State::Sx;
+								}
+								dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
+							}
 						}
 					}
 					log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());