diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 11:27:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 11:27:10 -0800 |
| commit | 9a892199f72bb08f78c868fe8ab5b8a63cf25f37 (patch) | |
| tree | 33647274e431863ab8d3cab998a56b8115498de0 /passes | |
| parent | e75ca29b19e230bc829a369c7de9cbadb629f5a7 (diff) | |
| download | yosys-9a892199f72bb08f78c868fe8ab5b8a63cf25f37.tar.gz yosys-9a892199f72bb08f78c868fe8ab5b8a63cf25f37.tar.bz2 yosys-9a892199f72bb08f78c868fe8ab5b8a63cf25f37.zip | |
Suppress warning message for init[i] = 1'bx
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sat.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430bba1e8..436ac1b01 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -269,7 +269,8 @@ struct SatHelper for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { - removed_bits.append(bit); + if (rhs[i] != State::Sx) + removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; |