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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:28:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:28:07 -0800 |
| commit | 588a713b5443ee4cec8479808a19785c9eadcc23 (patch) | |
| tree | e66786940d33b0d1ab299568716a7b88443a538b /passes | |
| parent | b951ca9e1c25b0c9c021419c3e537c743dca6216 (diff) | |
| parent | 4656f202c6f05d126c1acc79fca675e467c80840 (diff) | |
| download | yosys-588a713b5443ee4cec8479808a19785c9eadcc23.tar.gz yosys-588a713b5443ee4cec8479808a19785c9eadcc23.tar.bz2 yosys-588a713b5443ee4cec8479808a19785c9eadcc23.zip | |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 816c0276a..a686bbd32 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -754,15 +754,6 @@ void reintegrate(RTLIL::Module *module) c.wire = module->wires_.at(remap_name(c.wire->name)); newsig.append(c); } - - auto it = existing_cell->connections_.find(port_name); - if (it == existing_cell->connections_.end()) - continue; - if (GetSize(newsig) > GetSize(it->second)) - newsig = newsig.extract(0, GetSize(it->second)); - else - log_assert(GetSize(newsig) == GetSize(it->second)); - cell->setPort(port_name, newsig); if (w->port_input && !abc9_flop) |