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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
| commit | e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 (patch) | |
| tree | f41b454d90ffdff2f08a625cf36932805f3ee8d8 /passes | |
| parent | cfb0366a18b0f3cab254636fdf534a3de76af8d5 (diff) | |
| download | yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.gz yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.bz2 yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.zip | |
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index d458dce46..0053c8872 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -127,7 +127,7 @@ struct Ice40WrapCarryPass : public Pass { lut->setParam(ID(WIDTH), 4); lut->setParam(ID(LUT), cell->getParam(ID(LUT))); auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 }); + lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) }); lut->setPort(ID(Y), cell->getPort(ID(O))); Const src; |