Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Fix handling of src attributes in flatten | Clifford Wolf | 2018-03-10 | 1 | -7/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "memory_nordff" pass | Clifford Wolf | 2018-03-06 | 2 | -0/+112 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix connwrappers help message | Clifford Wolf | 2018-03-04 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add $dlatchsr support to clk2fflogic | Clifford Wolf | 2018-02-26 | 1 | -4/+25 |
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* | Fix opt_rmdff handling of $dlatchsr | Clifford Wolf | 2018-02-26 | 1 | -0/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Recognize stand-alone obj pattern even when it contains a slash | Clifford Wolf | 2018-02-13 | 1 | -0/+3 |
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* | Improve log messages in equiv_make | Clifford Wolf | 2018-01-19 | 1 | -2/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -0/+20 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 7 | -0/+12 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Bugfix in hierarchy blackbox module port width handling | Clifford Wolf | 2018-01-07 | 1 | -1/+2 |
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* | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -5/+4 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #480 from Fatsie/liberty_value_expression | Clifford Wolf | 2018-01-04 | 1 | -2/+22 |
|\ | | | | | Value of properties can be expression. | ||||
| * | Value of properties can be expression. | Staf Verhaegen | 2018-01-03 | 1 | -2/+22 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done. | ||||
* | | Temporarily derive blackbox modules in hierarchy to evaluate port widths | Clifford Wolf | 2018-01-04 | 1 | -1/+14 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix a bug in clk2fflogic memory handling | Clifford Wolf | 2017-12-14 | 1 | -1/+1 |
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* | Add clk2fflogic memory support | Clifford Wolf | 2017-12-14 | 1 | -1/+77 |
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* | Check for memories in clk2fflogic | Clifford Wolf | 2017-12-13 | 1 | -0/+5 |
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* | Add warnings for driver-driver conflicts between FFs (and other cells) and ↵ | Clifford Wolf | 2017-12-12 | 2 | -3/+11 |
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* | Add support for editline as replacement for readline | Clifford Wolf | 2017-11-08 | 1 | -0/+4 |
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* | Add "ltp" command | Clifford Wolf | 2017-10-31 | 2 | -0/+186 |
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* | Fix memory corruption bug in opt_rmdff | Clifford Wolf | 2017-10-26 | 1 | -0/+3 |
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* | Fix typo in opt_clean log message | Clifford Wolf | 2017-10-26 | 1 | -1/+1 |
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* | Revert 90be0d8 as it causes endless loops for some designs | Clifford Wolf | 2017-10-14 | 1 | -1/+0 |
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* | Fix input vector for reduce cells. | Kaj Tuomi | 2017-10-12 | 1 | -0/+1 |
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* | Rewrite ABC output to include proper net names in timing report | Clifford Wolf | 2017-10-10 | 1 | -2/+17 |
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* | Add blackbox command | Clifford Wolf | 2017-10-04 | 2 | -0/+82 |
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* | Added missing "break" | Andrew Zonenberg | 2017-09-15 | 1 | -0/+1 |
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* | Implemented off-chain support for extract_reduce | Andrew Zonenberg | 2017-09-15 | 1 | -84/+157 |
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* | extract_reduce now only removes the head of the chain, relying on "clean" to ↵ | Andrew Zonenberg | 2017-09-15 | 1 | -9/+19 |
| | | | | delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. | ||||
* | Merge pull request #412 from azonenberg/reduce-fixes | Clifford Wolf | 2017-09-14 | 1 | -2/+2 |
|\ | | | | | extract_reduce: Fix segfault on "undriven" inputs | ||||
| * | extract_reduce: Fix segfault on "undriven" inputs | Robert Ou | 2017-09-14 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | This is easily triggered when un-techmapping if the technology-specific cell library isn't loaded. Outputs of technology-specific cells will be seen as inputs, and nets using those outputs will be seen as undriven. Just ignore these cells because they can't be part of a reduce chain anyways. | ||||
* | | Merge pull request #411 from azonenberg/counter-extraction-fixes | Clifford Wolf | 2017-09-14 | 1 | -47/+116 |
|\ \ | | | | | | | Various improvements and bug fixes to extract_counter | ||||
| * | | Fixed bug where counter extraction on non-GreenPAK devices incorrectly ↵ | Andrew Zonenberg | 2017-09-14 | 1 | -32/+27 |
| | | | | | | | | | | | | handled parallel counter output | ||||
| * | | Added support for inferring counters with reset to full scale instead of zero | Andrew Zonenberg | 2017-09-14 | 1 | -4/+11 |
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| * | | Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. | Andrew Zonenberg | 2017-09-14 | 1 | -0/+1 |
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| * | | Added support for inferring counters with active-low reset | Andrew Zonenberg | 2017-09-14 | 1 | -6/+15 |
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| * | | Initial support for extraction of counters with clock enable | Andrew Zonenberg | 2017-09-14 | 1 | -9/+66 |
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| * | | Fixed typo in comment. Fixed bug where extract_counter would create up ↵ | Andrew Zonenberg | 2017-09-14 | 1 | -2/+2 |
| |/ | | | | | | | counters when it meant to create down counters. | ||||
* | | Minor changes to opt_demorgan requested during code review | Andrew Zonenberg | 2017-09-14 | 2 | -18/+18 |
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* | | Initial version of opt_demorgan is functioning for AND/OR gates. Not the ↵ | Andrew Zonenberg | 2017-09-12 | 2 | -0/+203 |
|/ | | | | prettiest results for bus inputs, but this can be improved | ||||
* | Add src attribute to extra cells generated by proc_dlatch | Clifford Wolf | 2017-09-09 | 1 | -7/+9 |
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* | Further improve extract_fa (but still buggy) | Clifford Wolf | 2017-09-02 | 1 | -28/+91 |
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* | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-09-01 | 2 | -0/+583 |
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| * | extract_counter: Added optimizations to remove unused high-order bits | Andrew Zonenberg | 2017-08-30 | 1 | -16/+34 |
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| * | extract_counter: Minor changes requested to comply with upstream policy, ↵ | Andrew Zonenberg | 2017-08-30 | 1 | -3/+4 |
| | | | | | | | | fixed a few typos | ||||
| * | Finished refactoring counter extraction to be nice and generic. Implemented ↵ | Andrew Zonenberg | 2017-08-28 | 1 | -11/+25 |
| | | | | | | | | techmapping from $__COUNT_ to GP_COUNTx cells. | ||||
| * | Refactored extract_counter to be generic vs GreenPAK specific | Andrew Zonenberg | 2017-08-28 | 1 | -51/+87 |
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| * | Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ↵ | Andrew Zonenberg | 2017-08-28 | 2 | -0/+514 |
| | | | | | | | | techmap/ since it's going to become a generic pass | ||||
* | | Update more stuff to use get_src_attribute() and set_src_attribute() | Clifford Wolf | 2017-09-01 | 1 | -4/+4 |
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