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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-12 17:13:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-12 17:13:27 +0100 |
| commit | ca2adc30c9f3736ccd9e381bbca43326e1f54a69 (patch) | |
| tree | 4381e9abac931751b36ac7a4ece1914a3a9a2094 /passes | |
| parent | ba90e08398e3068a525c3704a069182a365474e8 (diff) | |
| download | yosys-ca2adc30c9f3736ccd9e381bbca43326e1f54a69.tar.gz yosys-ca2adc30c9f3736ccd9e381bbca43326e1f54a69.tar.bz2 yosys-ca2adc30c9f3736ccd9e381bbca43326e1f54a69.zip | |
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 9 | ||||
| -rw-r--r-- | passes/proc/proc_dff.cc | 5 |
2 files changed, 11 insertions, 3 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 2d2ffa9a1..25d462ada 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -91,9 +91,16 @@ void rmunused_module_cells(Module *module, bool verbose) Cell *cell = it.second; for (auto &it2 : cell->connections()) { if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first)) - for (auto bit : sigmap(it2.second)) + for (auto raw_bit : it2.second) { + if (raw_bit.wire == nullptr) + continue; + auto bit = sigmap(raw_bit); + if (bit.wire == nullptr) + log_warning("Driver-driver conflict for %s between cell %s.%s and constant %s in %s: Resolved using constant.\n", + log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module)); if (bit.wire != nullptr) wire2driver[bit].insert(cell); + } } if (keep_cache.query(cell)) queue.insert(cell); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 98653dc6b..f732baa17 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -322,6 +322,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } } + SigSpec sig_q = sig; ce.assign_map.apply(insig); ce.assign_map.apply(rstval); ce.assign_map.apply(sig); @@ -350,13 +351,13 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) else if (!rstval.is_fully_const() && !ce.eval(rstval)) { log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval)); - gen_dffsr(mod, insig, rstval, sig, + gen_dffsr(mod, insig, rstval, sig_q, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.as_const(), sig, + gen_dff(mod, insig, rstval.as_const(), sig_q, sync_edge && sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge ? sync_edge->signal : SigSpec(), |