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| author | Kaj Tuomi <kaj.tuomi@siru.fi> | 2017-10-12 13:05:10 +0300 |
|---|---|---|
| committer | Kaj Tuomi <kaj.tuomi@siru.fi> | 2017-10-12 13:05:10 +0300 |
| commit | 90be0d800b350da12689c7943800e18420149eaa (patch) | |
| tree | 1913698f4a066f200938248e171d566d50c48ddb /passes | |
| parent | 2b03a73a460a2033f8944c7c85623cef11600024 (diff) | |
| download | yosys-90be0d800b350da12689c7943800e18420149eaa.tar.gz yosys-90be0d800b350da12689c7943800e18420149eaa.tar.bz2 yosys-90be0d800b350da12689c7943800e18420149eaa.zip | |
Fix input vector for reduce cells.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index eb9d02ad5..10bdf7221 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -88,6 +88,7 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { + new_sig_a.sort_and_unify(); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; total_count++; |